Circuit and method for evaluating the performance of an adaptive decision feedback equalizer-based serializer deserializer and serdes incorporating the same

ABSTRACT

A circuit and method for evaluating serializer deserializer (SERDES) performance that is particularly advantageous when the SERDES has a decision feedback equalizer (DFE). In one embodiment, the circuit has a data processing path and an operational feedback loop coupled to said data processing path and containing an equalizer, perhaps a DFE. In that embodiment, the circuit includes an eye scanning circuit coupled to said data processing path but separate from said equalizer and configured to measure at least one dimension of an eye relative to which said equalizer is configured for operation without substantially affecting said operation.

TECHNICAL FIELD OF THE INVENTION

The present invention is directed, in general, to data communications and, more specifically, to a circuit and method for evaluating the performance of an adaptive decision feedback equalizer (DFE)-based serializer/deserializer (SERDES) and a SERDES that incorporates the system or the method.

BACKGROUND OF THE INVENTION

High speed serial links operating at over 3 gigabits per second (Gbs) over distances in excess of several feet using only copper traces on conventional FR-4 dielectric printed circuit board (PCB) electrical backplanes have become commonplace. In fact, transceivers operating at rates in excess of 6 Gbs over similar PCB-based serial links are now becoming available in the marketplace. It is expected that rates of 10 Gbs will soon be introduced.

Such serial links commonly employ a serializer deserializer (SERDES) at each end for multiplexing and demultiplexing multiple, M-ary pulse amplitude modulated (M-PAM) non-return-to-zero (NRZ) high speed data streams. As the bit rates (and concomitant frequencies) have escalated over time, system designers have had to contend with the difficulty of communicating over these increasingly dispersive links without sacrificing system performance. As bit rates increase, intersymbol interference (ISI) and noise caused by crosstalk from other signals on the PCB increases. The signal-to-noise ratio (SNR) decreases due to the ISI and the noise to the point that discerning the boundary between adjacent received symbols at the receiver end becomes quite difficult. As a result, recovering a clock signal may become difficult, and bit error rates (BER) may rise to an unacceptable level as a result.

As those skilled in the art well understand, an oscilloscope trace of the serial link at the receiver end reveals overlapping, phase-shifted M-PAM NRZ waveforms with intermittent gaps, colloquially called “data eyes,” between the waveforms. The dimensions of each data eye, both horizontal (time) and vertical (voltage), diminish as dispersion increases and collapse at the extreme. To recover clock and data signals from the symbols correctly, the SERDES should accurately track the waveforms in terms of both time and voltage. The best opportunity to do this occurs by operating in the center of data eye, where adjacent symbols are best discriminated from one another.

The current trend in SERDES design is to gravitate toward techniques more commonly encountered in digital communications system design: increased reliance on signal processing and statistical system characterization. One of the more prominent examples of this design philosophy is evident in the application of channel equalization to combat the increased frequency selectivity of the channel. Proper channel equalization maximizes the effective dimensions of the data eye, affording the SERDES the best chance of interpreting symbols correctly.

It is important to determine that new SERDES designs and systems incorporating such SERDES designs are working optimally. Proper equalizer performance evaluation dictates that both the horizontal and vertical dimensions of the recovered data eye be measured and compared against expected operating conditions, including the recovered clock location in the data eye and the voltage sensitivity of the receiver. Misequalization problems can thus be corrected before the designs are put into production. In addition, SERDES and system margins can be measured during operation.

The typical technique for evaluating the performance of a SERDES is to scan the data eye to find its boundaries by varying the offset voltage and clock signal phase at which the SERDES is sampling the incoming waveforms. The boundary of the data eye is encountered when the BER rises to a threshold level. Unfortunately, this technique is of no use whatsoever if a SERDES is equipped with an equalizer that is a decision feedback equalizer (DFE).

The DFE (see, Austin, “Decision-Feedback Equalization for Digital Communication Over Dispersive Channels,” MIT Lincoln Laboratory, Tech. Report No. 437, August 1967, incorporated herein by reference) has become very popular in communications system design due to its effectiveness under a wide variety of channel types. The DFE is a nonlinear equalizer and is especially effective on channels with severe dispersion, because it can correct for channel imperfections without displaying the excessive noise enhancement of a linear equalizer. A DFE has a precursor (or feedforward) equalizer and a postcursor (or feedback) equalizer. The precursor equalizer is a linear transversal filter, the purpose of which is to cancel precursor intersymbol interference (ISI). The precursor equalizer does this by filtering the channel output, attempting to relocate most of the channel precursor energy to the postcursor response of the filtered output.

The postcursor equalizer is strictly causal. The postcursor equalizer uses past decisions to cancel the remaining postcursor ISI from the current decision variable. Unfortunately, because the postcursor equalizer bases subsequent decisions on earlier decisions, the varying of offset voltage and clock signal phase that occurs when scanning the data eye confuses the DFE; an incorrect symbol decision degrades subsequent symbols. The result is an inaccurate assessment of the SERDES's performance. In addition, the timing of the feedback decisions is critical in a DFE, especially at high data rates. This prevents the arbitrary movement of the clock position within the data eye.

What is needed in the art is a more generally applicable way to test equalizer-based SERDES. More specifically, what is needed in the art is a way to test DFE-based SERDES. Even more specifically, since many SERDES are now embodied in integrated circuits (ICs), what is needed in the art is a way to test DFE-based SERDES ICs with relatively few architectural changes or little additional hardware.

SUMMARY OF THE INVENTION

The present invention is based on the recognition that prior art equalizer performance evaluation techniques are inadequate because they can interfere with the operation of the equalizer, particularly if the equalizer is a DFE. The voltage offset and clock signal phase adjustments required to scan a data eye impair the decision-making ability of the equalizer, altering its performance and rendering the overall performance evaluation suspect. In response, the present invention introduces the broad concept of separating the eye measuring (“scanning”) circuitry from the equalizer so the former does not interfere with the latter.

In one aspect, the present invention provides a circuit for evaluating the performance of a SERDES, particularly one that has a DFE. In one embodiment, the circuit has a data processing path and an operational feedback loop coupled to the data processing path and containing the equalizer. In that embodiment, the circuit includes an eye scanning circuit coupled to the data processing path but separate from the equalizer and configured to measure at least one dimension of a data eye relative to which the equalizer is configured for operation without substantially affecting the operation.

In another aspect, the present invention provides a method of evaluating the performance of a SERDES. In one embodiment, the method includes: (1) measuring, with an eye scanning circuit coupled to the data processing path but separate from the equalizer, at least one dimension of a data eye relative to which the equalizer is configured for operation without substantially affecting the operation and (2) evaluating the performance based on the at least one dimension.

In yet another aspect, the present invention provides a SERDES incorporating the system for evaluating the SERDES's performance. In one embodiment, the SERDES includes: (1) a transmitter portion, and a receiver portion associated with the transmitter portion. The receiver portion has (1) a data processing path having a phase-locked loop (PLL) and a serial to parallel converter associated with the PLL, (2) an operational feedback loop coupled to the data processing path and containing a DFE and (3) a circuit for evaluating equalizer performance having an eye scanning circuit coupled to the data processing path but separate from the equalizer and configured to measure at least one dimension of a data eye relative to which the DFE is configured for operation without substantially affecting the operation.

The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a block diagram of a SERDES containing an adaptive DFE and incorporating a circuit or method for evaluating the performance of the SERDES constructed or carried out according to the principles of the present invention;

FIG. 2 illustrates a more detailed block diagram of the circuit of FIG. 1;

FIG. 3 illustrates a block diagram of a particular embodiment of the circuit of FIG. 2; and

FIG. 4 illustrates a flow diagram of a method of evaluating the performance of a SERDES carried out according to the principles of the present invention.

DETAILED DESCRIPTION

Referring initially to FIG. 1, illustrated is a block diagram of a SERDES incorporating an adaptive DFE and a circuit or method for evaluating the performance of the SERDES constructed or carried out according to the principles of the present invention. Those skilled in the pertinent art are generally familiar with the structure and function of a SERDES, and so they will not be set forth in great detail herein, except to the extent that they directly bear on an understanding of the present invention.

The SERDES includes a transmitter portion 100 and a receiver portion 155. A phase-locked loop (PLL) 105 in the transmitter portion 100 receives and stabilizes a clock signal (“CLOCK”) and possibly generates a higher frequency clock signal from CLOCK. A parallel to serial converter 110 receives parallel input data (“DATA IN”) and the stabilized clock signal from the PLL 105. The parallel to serial converter 110 converts the parallel data operating at a relatively low bit rate to a serial bit stream operating at a higher bit rate. For example, if the parallel data is N bits wide at data rate R, the serial data resulting from conversion will be a single signal operating at a rate N×R. The parallel to serial converter provides serial data output to an output amplifier 115, which drives a properly terminated (via a termination 120) high speed serial link 125 with serial non-return-to-zero (NRZ) data.

A properly terminated (via a termination 140) high speed serial link 135 (which may be the same as the high speed serial link 125) carrying serial NRZ data leads to an isolation amplifier 145 in the receiver portion 155. Serial data provided from the isolation amplifier 145 is provided to a clock and data recovery (CDR) circuit 150 and a serial to parallel converter 160. The CDR circuit 150 recovers the clock signal embedded in the serial data, uses it to retrieve the received serial data and provides the recovered clock signal and the data to the serial to parallel converter 160. The serial to parallel converter converts the serial data into parallel data (“DATA OUT”), analogous to the operation of the parallel to serial converter.

The illustrated embodiment of the circuit for evaluating equalizer performance of the present invention is located proximate a decision feedback equalizer (DFE) that is part of the CDR and serial to parallel converter 160 in the receiver portion 155. Those skilled in the pertinent art should understand, however, that the present invention can be used with equalizers other than DFEs.

Turning now to FIG. 2, illustrated is a more detailed block diagram of the circuit of FIG. 1. The serial to parallel converter 160 is illustrated as having a data processing path 200. The data processing path 200 includes one or more input data samplers 205 that sample serial NRZ data (“SERIAL NRZ DATA”) at instances defined by particular clock signal edges. The one or more input data samplers 205 provide their output, which now takes the form of a digital data stream, to a CDR circuit 210. The CDR circuit 210 recovers a clock signal from the digital data stream. The clock signal is used to drive the one or more input data samplers 205 and further to synchronize downstream circuitry (not shown).

The illustrated embodiment of the present invention introduces a pattern identifier and error counter 220 into the circuit. The purpose of the pattern identifier and error counter 220 is to evaluate the recovery of test patterns by determining the BER during testing. The digital data stream travels from the CDR circuit 210 through the serial to parallel converter 160 and into the pattern identifier and error counter 220, which attempts to recognize valid test patterns in the digital data stream. In the illustrated embodiment, these patterns are used for system and device-level testing. The data processing path 200 includes a multiplexer 215 interposing the CDR circuit 210 and the pattern identifier and error counter 220. The purpose and operation of the multiplexer 215 will be set forth below.

The serial to parallel converter 160 further includes an operational feedback loop 225. The operational feedback loop 225 is coupled to the data processing path 200 and includes an equalizer 230 (which is a DFE in one embodiment). The equalizer 240 receives the digital data stream and produces from it a signal that is fed back and combined with the serial NRZ data to improve its quality and BER. Those skilled in the pertinent art are familiar with the various types of equalizers, including DFEs, and their operation. Such will therefore not be described in greater detail herein.

As described above, it is important to verify that the SERDES is operating within the eye of the serial NRZ data and to determine voltage and timing margins. Verifying SERDES operation means scanning the data eye to determine its dimensions. Unfortunately, scanning the data eye can cause the equalizer 240 to malfunction, artificially increasing BER. This is because prior art eye scanning circuitry was integrated into the operational feedback loop 225 and therefore interfered with its operation. The present invention seeks to remedy this problem.

Accordingly, the serial to parallel converter 160 introduces an eye scanning circuit 235. The eye scanning circuit 235 is coupled to the data processing path 200 but is separate from at least the equalizer 230 (and, in the illustrated embodiment, the entire operational feedback loop 225). The eye scanning circuit 235 is configured to measure at least one dimension of a data eye relative to which the equalizer 230 is configured for operation. This it does without substantially affecting the equalizer's operation.

Accordingly, the eye scanning circuit 235 includes one or more secondary data samplers 245. The one or more secondary data samplers operate just as the one or more input data samplers 205; they convert the serial NRZ data into a secondary digital data stream. The one or more secondary data samplers 245 do not affect the operation of the one or more input data samplers 205. Thus, the secondary digital data stream produced by the one or more secondary data samplers 245 does not interact with the digital data stream produced by the one or more input data samplers 205.

The digital data stream is received by the multiplexer 215, which allows the secondary digital data stream to be pattern-verified and error-counted in the pattern verifier and error counter 220. The operation of the multiplexer 215 will be further described below.

Eye scanning is effected in the illustrated embodiment by two circuits within the eye scanning circuit 225: a voltage offset circuit 240 and a phase shifting circuit 250. The voltage offset circuit 240 is coupled to the input of the one or more secondary data samplers 245. The voltage offset circuit 240 applies a controlled offset voltage to the serial NRZ data to bias it before it is delivered to the one or more secondary data samplers 245. It is apparent that the voltage bias shifts the serial NRZ data vertically with respect to the one or more secondary data samplers 245, effecting a vertical scan of the data eye contained in the serial NRZ data.

The phase-shifting circuit 250 is coupled to the output of the one or more secondary data samplers 245. The phase-shifting circuit phase-shifts (advances or delays) the clock signals used to sample the serial NRZ data and generate the secondary digital data stream emerging from the one or more secondary data samplers 245. It is apparent that phase-shifting shifts the sampling time instant of the one or more secondary data samplers 245 horizontally with respect to the point at which the one or more primary input data samplers 205 and CDR circuit 210 operate, effecting a horizontal scan of the data eye, now reflected in the secondary digital data stream.

The multiplexer 215 can operate in a number of possible ways. Verification of SERDES performance can occur while the SERDES is operating. To do so, the multiplexer 215 interleaves the digital data stream from the one or more input data samplers 205 with the secondary digital data stream from the one or more secondary data samplers 245. The pattern verifier and error counter 220 verifies patterns and counts errors contained in the secondary digital data stream advantageously but not necessarily reusing the circuits that normally validate the primary data path.

In an alternative embodiment, the SERDES is provided with a test mode that is separate from an operational mode. In the operational mode, the multiplexer 215 is set to deliver only the digital data stream from the one or more input data samplers 205 to the pattern verifier and error counter 220. In the test mode, the multiplexer 215 is set to deliver only the secondary digital data stream from the one or more secondary data samplers 205 to the pattern verifier and error counter 220.

Irrespective of whether verification occurs during operation or during a separate test mode, the BER, which is provided by the pattern verifier and error counter 220, is used to ascertain the dimensions of the data eye. Once the dimensions are determined, the operating point and effectiveness of the DFE and the SERDES (in terms of voltage offset, clock signal phase or both) can be compared and judged to be acceptable or not. Those skilled in the art are familiar with the standards applied to SERDES operation and validation.

Turning now to FIG. 3, illustrated is a block diagram of a very specific embodiment of the circuit of FIG. 2. The embodiment may be advantageous when the SERDES takes the form of an IC, because it uses hardware blocks that are already present in the SERDES for the purpose of verifying the SERDES's operation. The equalizer is shown as separate delay blocks (one of which is designated 332), filter coefficients (a₁, a₂, . . . , a_(n)) and DFE control circuits 334.

A voltage controlled oscillator 314 provides an initial clock signal (CLK1) to an intermediate phase interpolator 354, which shifts the phase of the initial clock signal to produce a second clock signal (CLK2). CLK2 is provided to the one or more secondary data samplers 245 and a synchronizer 359 to effect horizontal data eye scanning. CLK2 is also provided to a second phase interpolator 356 to be used in the clock and data recovery loop.

Clock signal dividers and a demultiplexer 312 provide candidate control signals to early/late voting logic 352. The early/late voting logic provides a winning control signal to phase select logic 316, which drives the second phase interpolator 356 that aligns the clocks used in the one or more input data samplers with respect to the serial NRZ data.

The intermediate phase interpolator 354 can generate an output clock signal with arbitrary delays with respect to the VCO output to either advance or retard the phase of CLK2. The second phase interpolator 356 also sees its reference clock signals shift phase whenever CLK2 moves. However, since this loop is locked to the incoming data stream, the CDR circuit (210 of FIG. 2) as a whole will have a natural tendency to restore the loop to its locked state.

For example, assume the intermediate phase interpolator 354 advances its output phase by t picoseconds (ps). This shifts CLK2 t ps further into the data eye and shifts the recovered clock signal(s) also by t ps. However, the clock and data recovery loop will recognize that the recovered clock signal(s) are now late in the data eye (assuming the loop was initially locked to the center) and will act to retard the recovered clock signal back into the center position by t ps.

The impact of the phase shift of CLK2 on the equalized data eye and data recovery is null since the input data sampling clock signals are all derived from the recovered clock signal. The net effect is a shift in the phase of CLK2 relative to the recovered, equalized data eye, providing the ability to scan the data eye horizontally. Ultimately, CLK1 is provided to a DFE re-timing block 318.

The vertical data eye measurement is provided by the voltage offset circuit 240, which includes an amplifier (not shown) with a programmable offset and a sense amplifier (not shown) that is used as a sampling element.

Turning now to FIG. 4, illustrated is flow diagram of a method of evaluating the performance of a SERDES carried out according to the principles of the present invention. The method begins in a start step 410 when evaluation of the operation of a SERDES is to be undertaken.

The method proceeds to a step 420 in which an eye scanning circuit that is coupled to the SERDES's data processing path but is separate from the SERDES's equalizer measures, by virtue of phase-shifting, a horizontal dimension of a data eye relative to which the equalizer is configured for operation without substantially affecting the operation of the equalizer. The method proceeds to a step 430 in which the eye scanning circuit measures, by virtue of voltage offset-shifting, a vertical dimension of the data eye, again without substantially affecting the operation of the equalizer. In a step 440, the performance of the SERDES is evaluated based on the at least one dimension (both dimensions in the exemplary method of FIG. 4).

While the method disclosed herein has been described and shown with reference to particular steps performed in a particular order, those skilled in the pertinent art will understand that these steps may be combined, subdivided, or reordered to form an equivalent method without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and/or the grouping of the steps are not limitations of the present invention.

Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form. 

1. A circuit for evaluating serializer deserializer (SERDES) performance, said SERDES having a data processing path and an operational feedback loop coupled to said data processing path and containing an equalizer, comprising: an eye scanning circuit coupled to said data processing path but separate from said equalizer and configured to measure at least one dimension of a data eye relative to which said equalizer is configured for operation without substantially affecting said operation.
 2. The circuit as recited in claim 1 wherein said equalizer is a decision feedback equalizer.
 3. The circuit as recited in claim 1 wherein said eye scanning circuit comprises a phase-shifting circuit and said at least one dimension is a horizontal dimension.
 4. The circuit as recited in claim 1 wherein said data processing path contains an input data sampler and said eye scanning circuit contains a secondary data sampler separate from said input data sampler.
 5. The circuit as recited in claim 3 wherein said phase-shifting circuit comprises a phase interpolator and phase shift logic configured to control said phase interpolator.
 6. The circuit as recited in claim 1 wherein said eye scanning circuit comprises a voltage offset circuit and said at least one dimension is a vertical dimension.
 7. The circuit as recited in claim 1 wherein said SERDES is embodied in an integrated circuit (IC) and said eye scanning circuit employs a demultiplexer and a pattern verifier and error counter located in said data processing path to evaluate said equalizer performance.
 8. A method of evaluating serializer deserializer (SERDES) performance, said SERDES having a data processing path and an operational feedback loop coupled to said data processing path and containing an equalizer, comprising: measuring, with an eye scanning circuit coupled to said data processing path but separate from said equalizer, at least one dimension of a data eye relative to which said equalizer is configured for operation without substantially affecting said operation; and evaluating said performance based on said at least one dimension.
 9. The method as recited in claim 8 wherein said equalizer is a decision feedback equalizer.
 10. The method as recited in claim 8 wherein said measuring is carried out in part with a phase-shifting circuit and said at least one dimension is a horizontal dimension.
 11. The method as recited in claim 8 wherein said data processing path contains an input data sampler and measuring is carried out in part with a secondary data sampler separate from said input data sampler.
 12. The method as recited in claim 10 wherein said measuring is carried out in part with a phase interpolator and phase shift logic configured to control said phase interpolator.
 13. The method as recited in claim 8 wherein said measuring is carried out in part with a voltage offset circuit and said at least one dimension is a vertical dimension.
 14. The method as recited in claim 8 wherein said SERDES is embodied in an integrated circuit (IC) and said evaluating is carried out in part with a demultiplexer and a pattern verifier and error counter located in said data processing path.
 15. A serializer deserializer (SERDES), comprising: a transmitter portion; and a receiver portion associated with said transmitter portion and having: a data processing path having a phase-locked loop (PLL) and a serial to parallel converter associated with said PLL, an operational feedback loop coupled to said data processing path and containing a decision feedback equalizer (DFE), and a circuit for evaluating a performance of said SERDES having an eye scanning circuit coupled to said data processing path but separate from said equalizer and configured to measure at least one dimension of a data eye relative to which said DFE is configured for operation without substantially affecting said operation.
 16. The SERDES as recited in claim 15 wherein said eye scanning circuit comprises a phase-shifting circuit and said at least one dimension is a horizontal dimension.
 17. The SERDES as recited in claim 15 wherein said data processing path contains an input data sampler and said eye scanning circuit contains a secondary data sampler separate from said input data sampler.
 18. The SERDES as recited in claim 16 wherein said phase-shifting circuit comprises a phase interpolator and phase shift logic configured to control said phase interpolator.
 19. The SERDES as recited in claim 15 wherein said eye scanning circuit comprises a voltage offset circuit and said at least one dimension is a vertical dimension.
 20. The SERDES as recited in claim 15 wherein said SERDES is embodied in an integrated circuit (IC) and said eye scanning circuit employs a demultiplexer and a pattern verifier and error counter located in said data processing path to evaluate said equalizer performance. 